Careers
ASIC Implementation & Low-Power Design Engineer
- Process node
- 12nm FinFET
- Primary RTL language
- VHDL
About the role
In this dual-impact role, you will take ownership of our low-power design methodology, enhancing and tightly integrating our power intent (CPF/UPF) and rail analysis flows into our existing 12nm tape-out pipeline. Additionally, you will take ownership of block-level digital implementation (synthesis, STA, CDC) for a suite of established IP blocks, freeing technical leadership to focus on top-level system architecture.
Key responsibilities
- Low-power methodology & flow enhancement: Review, harden, and fully integrate our power intent specifications (CPF/UPF) and static low-power check flows (e.g., Conformal Low Power) into the main EDA toolchain.
- Power & rail analysis: Perform static and dynamic IR drop analysis, electromigration (EM) checks, and power domain/clock-gating optimization on 12nm silicon.
- Block implementation ownership: Drive synthesis, timing constraints definition, static timing analysis (STA), and CDC analysis for several assigned digital IP blocks using existing floorplans.
- Top-level power integration: Work closely with top-level leads to ensure clean power domain isolation, level-shifter insertion, retention registers, and power-state sequencing.
- ECO & sign-off support: Perform timing closure and power sign-off checks for block-level handoffs to physical design.
Required qualifications
- Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
- Experience: 5+ years of hands-on digital ASIC design, synthesis, and low-power sign-off experience.
- Low-power standards: Proven expertise with power intent formats (CPF or UPF/IEEE 1801), power gating, multi-VDD, retention strategies, and isolation logic.
- Advanced process nodes: Direct experience working in FinFET nodes (12nm or below preferred).
- EDA toolchain proficiency: Deep experience with industry-standard synthesis (Genus), STA (Tempus), and power/rail analysis tools (Voltus).
- Implementation skills: Solid background in SystemVerilog/Verilog/VHDL, Tcl scripting for flow automation, and timing constraints (SDC).