Careers
ASIC Peripheral & SoC Integration Engineer
- Process node
- 12nm FinFET
- Primary RTL language
- VHDL
About the role
In this role, you will bridge the gap between silicon design and low-level software. You will own the complete lifecycle (RTL design, verification, register map creation, and driver development) for standard management and peripheral interfaces (I2C, SPI, MDIO, UART, GPIO) across our 12nm SoC architecture.
Key responsibilities
- Peripheral RTL design: Implement, configure, and integrate low-speed peripheral and control IPs (I2C, SPI, MDIO, etc.) into the main SoC interconnect.
- Block verification: Build block-level testbenches (SystemVerilog/VHDL/UVM or C/Assembly-based verification) to validate protocols, register behavior, and bus attachments.
- Driver development: Write clean, low-level drivers and bring-up code for hardware testing and software team handoff.
- SoC bus integration: Connect peripherals to on-chip buses and configure interrupt routing to the system controller/PLIC.
- Silicon bring-up support: Assist with FPGA emulation and post-silicon laboratory bring-up for control interface validation.
Required qualifications
- Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
- Experience: 3–6 years of experience in ASIC RTL design and embedded software integration.
- RTL & hardware: Solid proficiency in RTL for synthesizable design and verification.
- Interface standards: Deep understanding of standard serial and management protocols (SPI, I2C, MDIO/MDC, UART).
- Low-level C programming: Hands-on experience writing bare-metal drivers, register-level bit manipulation, and low-level hardware abstraction layers.
- Bus architectures: Familiarity with standard bus protocols (APB, AHB, AXI, TileLink) and register generation tools. Ability to interface to custom system fabric.