Junior ASIC Design Engineer
- Process node
- 12nm FinFET
- Primary RTL language
- VHDL
About the role
We are seeking a motivated Junior ASIC Design Engineer to join our engineering team. In this role, you will primarily focus on RTL implementation based on architectural specifications and technical descriptions to implement a state-of-the-art, cyber-hardened IP processor core. You will also gain valuable hands-on experience supporting our physical implementation team, helping to maintain constraints, run Clock Domain Crossing (CDC) checks, and execute block-level implementation in GlobalFoundries 12nm FinFET process using our existing automation scripts.
Additionally, you will play an active role in improving our design flow processes, identifying inefficiencies, and helping optimize our development pipeline as you grow with the team. This is an excellent opportunity for an early-career engineer to build a strong foundation in both front-end design and back-end implementation workflows.
Key responsibilities
- RTL implementation: Write clean, synthesizable, and efficient VHDL code based on functional specifications and design descriptions.
- Testbench and verification: Write self-checking testbenches, scripts and assembly-level code to validate designs pre-implementation.
- Design flow optimization: Actively participate in identifying, documenting, and improving design flow processes and scripting infrastructure to enhance team efficiency.
- Front-end verification support: Work closely with the verification team to debug RTL design issues and ensure block-level functionality.
- Physical implementation support: Assist with the physical design flow, including creating and refining timing constraints.
- Block-level implementation: Execute block-level synthesis and place-and-route tasks using existing company scripts and tool infrastructure.
Qualifications & skills
- Citizenship requirement: Due to the nature of our defense programs, US citizenship is required.
- Education: Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a closely related field.
- HDL languages: Strong foundational knowledge of VHDL.
- Digital design: Solid understanding of synchronous/asynchronous digital design concepts, state machines, and pipelining.
- Flows & scripting: Basic familiarity with scripting languages like Tcl, Python, Bash or Perl to run, modify, and improve automation scripts.
- Tool familiarity (plus): Exposure to standard EDA tools (e.g., Synopsys, Cadence, or Siemens) for synthesis, CDC, or simulation through internships or academic projects is highly desirable.